Looking for a HW/SW co-design expert to help us implement the inference of AI models on resource-constraint edge devices: The workload for the target AI application will need to be distributed on a group of AI accelerators having heterogeneous hardware architecture.
Tasks
- Lead the hardware/software co-design of custom AI accelerators targeting reconfigurable architectures (FPGAs, etc.).
- Design and optimize AI models (DNNs, LLMs, etc.) for low-latency, resource-constrained, and energy-efficient execution.
- Contribute to synthesis, optimization, and deployment of AI accelerators on switches, SmartNICs, heterogeneous HW accelerators in base stations.
- Develop distributed inference strategies for performing AI inference on resource-constrained AI accelerators.
- Lead the technical validation and prototyping with early adopters.
- Collaborate on grant writing, product roadmap, and tech strategy.
- Hire and mentor future engineers and researchers as the team grows.
Requirements
- Based in Germany, with a valid Niederlassungserlaubnis or German citizenship.
- A Master's or PhD in Computer Science, Electrical Engineering, or related fields in HW/SW Co-design.
- Experience with energy efficiency, sustainability, high-throughput, and other impactful design techniques and goals.
- Experience with distributed computing and orchestration techniques for distributed AI inference.
- Proven ability to build systems end-to-end: from prototype to deployable demo.
- Fluent in English; German is a bonus.
- A strong background and hands-on skills ib the following fields:
Machine Learning (SW side):
- Optimizing DNNs, LLMs, or other AI models for embedded / edge devices.
- Quantization, pruning, knowledge distillation, or other optimziation methods.
Hardware Design:
- Designing and synthesizing AI accelerators for FPGAs or custom ASICs.
- Circuit-level optimization, High-Level Synthesis (HLS), or RTL design experience.
Benefits
Non-paid job at the moment, equity share at the time of founding the company is considered.